Semiconductor device technology is increasingly relying on specialty Si-based substrates to improve the performance of complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs). For example, the strong dependence of carrier mobility on silicon orientation has led to increased interest in hybrid orientation Si substrates in which nFETs are formed in (100)-oriented Si (the orientation in which electron mobility is higher) and pFETs are formed in (110)-oriented Si (the orientation in which hole mobility is higher), as described, for example, by M. Yang, et al. “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEDM 2003 Paper 18.7 and U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003 entitled “High-performance CMOS SOI devices on hybrid crystal-oriented substrates”.
While there are a variety of approaches for fabricating hybrid orientation substrates, all share a fundamental requirement for some type of bonding and layer transfer to produce regions of semiconductor with a first orientation (derived from a first semiconductor wafer) and regions of semiconductor with a second orientation (derived from a second semiconductor wafer).
Most Si wafer bonding techniques utilize hydrophilic bonding, in which an oxide (or native oxide) is disposed on both of the wafer surfaces to be bonded. Hydrophilic bonding is a suitable approach when an oxide is desired at the bonded interface (for example, when fabricating silicon-on-insulator (SOI) substrates). However, some applications require direct Si-to-Si bonding, with no oxide layer at the bonded interface. For example, fabrication of hybrid orientation substrates by amorphization/templated recrystallization (ATR) methods such as described, for example, by U.S. patent application Ser. No. 10/725,850, filed Dec. 2, 2003 entitled “Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers” requires a clean Si/Si interface between Si surfaces having different surface orientations (e.g., (110) Si and (100) Si).
Such direct Si-to-Si bonding is normally achieved with hydrophobic bonding, a more difficult and less well developed technique than the more commonly used hydrophilic bonding. Hydrophobic bonding is a relatively difficult technique for several reasons. Hydrophobic (H-terminated) surfaces are more easily contaminated than hydrophilic ones, often leading to a choice to perform hydrophobic bonding in a vacuum environment. In addition, the widely used surface plasma treatments developed to allow room temperature bonding typically introduce surface oxygen, making them incompatible with an oxide-free bonded interface. Bonding at higher temperatures also can present difficulties, since most cleaving processes (used to separate the bonded layer from the wafer to which it was originally attached) are thermally activated and start occurring in the same temperature range as the bonding.
Direct Si-to-Si wafer bonding could be greatly simplified if one had a “quasi-hydrophobic” bonding method in which an ultrathin (1-2 nm) oxide would be present on one or both wafer surfaces during bonding (allowing the bonding to be hydrophilic), but made to disappear by removing it after the bonding to leave the desired direct Si-to-Si contact at the bonded interface.
The dissolution and/or islanding of buried oxide layers between bonded Si wafers has been examined previously as a function of Si wafer doping, Si wafer growth (float-zone (FZ) or Czochralski (Cz)), and Si wafer surface orientation. Both P. McCann, et al. “An investigation into interfacial oxide in direct silicon bonding,” 6th Int. Symp. on Semiconductor Wafer Bonding, San Francisco, Sep. 2-7, 2001, and K.-Y. Ahn, et al. “Stability of interfacial oxide layers during silicon wafer bonding,” J. Appl. Phys. 65 561 (1989) utilized N2 annealing at temperatures in the range from 1100°-1200° C. It was concluded that dissolution of native oxides having a thickness greater than 1 nm is not possible, and that undesirable oxide islanding is typical, especially with Cz wafers.
An example of this islanding is shown schematically in FIGS. 1A-1B. FIG. 1A shows a cross section view of a bonded structure 10 before an anneal that produces islanding. Bonded structure 10 in FIG. 1A comprises a substrate silicon wafer 20, a bonded silicon layer 30, and a continuous oxide layer 40 at an interface 50. After annealing, the oxide layer 40 breaks up into islands 60, as shown in FIG. 1B.
In contrast to these results, it was shown that a few monolayers of interfacial oxide could be made to disappear in FZ wafers after annealing at 1150° C. Unfortunately, FZ wafers are still very expensive, are relatively easily deformed during processing, and typically are used only in cases where high resistivity substrates are required. Moreover, it is expected that interfacial oxide layers will never be as thin as a few monolayers, if the bonding is done in any environment other than high vacuum.
In view of the above, it would be desirable to have a method for removing the ultrathin interfacial oxide remaining at the Si—Si interface after bonding. More particularly, it would be desirable to have a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding.